| Summary: | 博士 === 國立清華大學 === 電機工程學系 === 102 === Through-Silicon Vias (TSVs) are high-density vertical interconnects between dies and they enable the creation of three-dimensional Integrated Circuits (3D-ICs) having higher performance and lower power consumption than traditional 2D-ICs. Currently, a practical TSV-based 3D integration approach is to place multiple dies (or die stacks) side-by-side on a passive silicon interposer base, in which there are TSVs and metal wires serving as interconnects; this is also referred to as 2.5D integration. In this thesis, we propose a Design-for-Test (DfT) architecture and a test strategy for post-bond testing of such interposer-based 3D-ICs. The architecture enables testing of external interconnects and die-internal circuits after dies and interposer are bonded together. We present various parallel (multi-bit) Test Access Mechanism (TAM) architectures, which aim to achieve short test times. Functional interconnects and package pins are reused to build the parallel TAM to minimize the test cost. For different TAM architectures, we propose corresponding optimization algorithms to help identify the best TAM configuration with the shortest test time. We also propose an “adding-wire” approach that can further reduce test time at the expense of extra test-dedicated interconnects between dies. Experimental results show that the proposed techniques are effective in test time reduction. Moreover, cost analysis is conducted and the results suggest that our approaches have lower costs compared with a base-case one-bit JTAG-only solution.
One of the most important factors that affect the yield of interposer-based 3D-ICs is the integrity of interconnects which connect various dies. Therefore, the second part of this thesis focuses on 3D-IC interconnect testing, diagnosis, and repair. We propose an interconnect redundancy architecture and a methodology for 1) detecting faulty 3D-IC interconnects, 2) identifying open defect locations within interconnects to improve defect diagnosis resolution, and 3) repairing the open interconnects to improve yield. We also propose a Built-In Self-Test (BIST) scheme which can improve test quality by enabling at-speed interconnect testing. Experimental results show that the 3D-IC yield gain achieved by the proposed interconnect repair scheme ranges from 0% to 13%, depending on different open defect ratio and interposer yield. For higher open defect ratio and lower interposer yield, the yield gain is higher. The area cost of the proposed BIST design is small. In addition, cost analysis results suggest that although the proposed interconnect repair approach induces extra costs, the net profit is higher than that without repair.
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