Power-Efficient CT ΣΔ Audio Modulator Design Using Numerical Optimization Methodology

• Main Authors: Chen, Wei-Lin, 陳韋霖
• Other Authors: Hsieh, Chih-Cheng
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/72714605592602060071

博士 === 國立清華大學 === 電機工程學系 === 102 === This thesis proposes a method for the discretization of continuous-time sigma-delta modulators (CT-ΣΔMs) with various circuit nonidealities. Recurrence equations for the sampled states of a CT-ΣΔM are derived to find the equivalent discrete-time (DT) transfer functions of CT loop filters along with several second-order effects, such as finite DC gain, finite unity-gain bandwidth (GBW) of an amplifier, and excess loop delay (ELD), etc. This allows a synthesis flow that considers these nonidealities at the system level. The proposed approach generalizes existing works relating to the DT modeling of a CT-ΣΔM, and is applicable to arbitrary-order loop filters with unconstrained digital-to-analog converter (DAC) output waveforms. According to the DT model, a third-order low-pass modulator design based on a numerical optimization shows that the second-order effects of a CT-ΣΔM can be noticeably mitigated by the appropriate coefficient scaling. Based on this methodology, a low-voltage low-power third-order continuous-time sigma-delta modulator for audio applications is designed. For low-voltage operation, the modulator employs an input-signal-feedforward architecture and a 1.5-bit quantizer to reduce the internal signal swings in a loop filter. The loop filter coefficients are synthesized based on a numerical optimization to minimize in-band quantization noise power, noticeably relaxing op-amp requirements and saving power consumption. For operating from a sub-0.5-V supply voltage, a pseudo-differential inverter-based single-stage op-amp incorporating a bulk-driven common-mode feedback (CMFB) circuit is developed. The quantizer is implemented with a bulk-driven multi-input regenerative latch to perform the feedforward coefficients and summing. The prototype modulator is fabricated in 90-nm CMOS technology, achieving an 80.2-dB peak dynamic range and a 77.1-dB peak SNDR over a 20-kHz bandwidth. The modulator occupies core area of 0.14-mm2 and dissipates only 9.1-μW from a 450-mV power supply. The figure of merit (FoM) of overall modulator is 39-fJ/conv-step, which is competitive to state-of-the-art designs.