Register allocation issues on highly distributed register file architectures

• Main Authors: Lu, Chia-Han, 呂佳翰
• Other Authors: 李政崑
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/79041638544275958381

博士 === 國立清華大學 === 資訊工程學系 === 102 === Embedded processors developed within the past few years have employed novel hardware designs to reduce the ever-growing complexity, power dissipation, and die area. While using distributed register file architecture is considered to have less read/write ports than using traditional unified register file structures, it presents challenges in compilation techniques to generate efficient codes for such architectures. Digital signal processors (DSPs) with very long instruction word (VLIW) data-path architectures are increasingly being deployed on embedded devices for multimedia processing applications. To reduce the power consumption and design cost of VLIW DSP processors, distributed register files and multi-bank register architectures are bein adopted to reduce the number of read and write ports associated with register files, which presents new challenges for devising compiler optimization schemes. Distributed register file architectures divide registers into multiple sets, and it leads to complicated communication and small register files. Complicated communication requires a new phase to handle it. Small register files increase spilling and reduce performance. The dissertation attempts to resolve these two issues. There are three primary results: - A heuristic method is proposed for global register file assignment making suitable decisions based on local register file assignment. The experimental results indicate that the compilation based on our proposed approach delivers performance improvements. - We address the issues of reducing the spill cost for a VLIW DSP with distributed register files. Spill code produced by register allocation is traditionally handled by memory spills, but the multibank register-file architecture provides the opportunity to spill-out register values onto different register banks. We present a framework to model the live ranges in different register banks, and treats register banks as optional spilling locations. - To reduce spilling possibly produced from the phase of register file assignment, we propose a method which attempts to improve spilling by estimating the spilling cost from two aspects: assignment and spilling. We report that the SPIFR method not only reduces spilling ratios but increases the performances. The results of all experiments performed using our optimizing compiler based on the Open64. The results of experiments showed the effectiveness of each of my methods.