Width Minimization in the Single-Electron Transistor Array Synthesis

• Main Authors: Liu, Chian-Wei, 劉千瑋
• Other Authors: Wang, Chun-Yao
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/53188790540861651573

碩士 === 國立清華大學 === 資訊工程學系 === 102 === Power consumption has become one of the primary challenges to meet the Moore’s law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultra-low power consumption in operation. Prior works have proposed automated mapping approaches for SET arrays which focus on minimizing the number of hexagons in SET arrays. However, the area of an SET array is the product of the bounded height and bounded width, and the height is usually equal to the number of inputs in the Boolean function. Consequently, in this work, we focus on the width minimization in the mapping of the SET arrays. Our approach consists of techniques of product term minimization, variable reordering, product term reordering and architecture relaxation. The experimental results show that the proposed approach saves 45\% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks.