Cluster-Based Interconnection Architecture for Multi-Core Processors

• Main Authors: Yang, Hui-Min, 楊惠敏
• Other Authors: Hwang, TingTing
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/52684059555609805079

碩士 === 國立清華大學 === 資訊工程學系 === 102 === With the rapid development of silicon technology, chip multiprocessor (CMP) are widely used for parallel applications and real-time applications. For CMPs, as the number of processors on a chip continues to increase, efficient communication is essential for achieving high performance and throughput. Therefore, the design of the interconnection architecture plays an important role in determining the performance, area, and power consumption of the overall system. Because network-on-chip (NoC) and traditional on-chip bus interconnection have their own advantages and disadvantages, we need to consider the system performance requirement and the application properties to design an appropriate network interconnection architecture. In this thesis, for CMPs and multi-threaded applications, we propose and evaluate three cluster-based interconnection architectures: (1) cluster-based NoC architecture, (2) hierarchical bus architecture, and (3) hybrid architecture. The experiment results show that considering both performance and scalability for CMPs and multi-threaded applications, cluster-based NoC architecture is the most practical choice among the three cluster-based interconnection architectures.