A Study of the Limits of Parallelism Available in SIMD Processors Through Register Packing
碩士 === 國立中山大學 === 資訊工程學系研究所 === 102 === This thesis designed an instruction-level-parallelism processor for the embedded system with general purpose computations. The hardware of the embedded system is small-scalar then currently popular CPU or GPU. We exploit some techniques to enhance the instruct...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/61446172694694401702 |