Design of Low-Power Phase-Locked Loop for Medical Implant Communication Service Band Applications

• Main Authors: Shi-Lin Wang, 王士霖
• Other Authors: Yu-Lung Lo
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/16159578109610042478

碩士 === 國立高雄師範大學 === 電子工程學系 === 102 === In the recent, the application of PLL in modern communication systems, such as Medical Implant Communication Service (MICS), GSM, GPS, WCDMA and wireless LANs grow quickly by the process of circuit design and fabricating. The application of frequency synthesizer which is used in wireless LANs systems. This work proposes a low-power PLL for Medical Implant Communication Service band applications. The operating range of MICS band is from 402MHz to 405MHz, and 10 channel space would be switched for data communicating. Every channel space has 300KHz bandwidth. Low power consumption is very important for MICS band of which application is suitable for implantable medical devices. In Section I introduce bulk bias techniques for low-voltage circuit, such as bulk-driven, body forward. Body forward techniques contain different approaches. One is bulk connect ground, and another is bulk connect gate. We not only use bulk-driven techniques on voltage controlled oscillators of analog circuits, but also make use of lower power bulk connect ground techniques on differential to single-ended converter of digital circuits. In Section II use the PLL theory to derive RC value of the second-order low-pass filter. We use Matlab/Simulink tools to simulate system stability of PLL, so that we can shorten the design time of PLL, and we complete Hspice simulation results for verification. In Section IV utilizes the proposed of low-power PLL for Medical Implant Communication Service band applications. In low voltage design strategies, this work propose a low power charge pump architecture and analyze two divider architecture to reduce power consumption and jitters. The most special point not only use bulk-driven techniques on voltage control oscillators but also make use of bulk connect ground techniques on differential to single-ended converter circuits. This work use low-voltage circuit techniques that bulk-driven and body forward bias, reducing the threshold voltage (VTH), so that the circuit can operate at low voltage 0.7V. Due to the process, voltage, and temperature (PVT) variations in IC fabrication, the proposed bulk-driven voltage control oscillator (BVCO) with twelve pmos capacitors has advantage of operating at low supply voltage. This work use the proposed manual calibration technique S0, S1 to adjust the capacitance of circuits, so that BVCO would change ouput frequency to compensate the effect of the PVT variations. The PLL can lock at 403MHz output frequency with the PVT variations in Medical Implant Communication Service band. The chip is implemented in TSMC 0.18 μm 1P6M CMOS process technology. The post-layout-simulation results have shown that the proposed a low-power PLL with chip area of 1.2mm×1.2mm, core area of 0.017mm2, operating frequency range from 398 MHz to 403 MHz, and power consumption of 0.683 mW at 403 MHz (excluding output buffer). Index Terms: Bulk-Driven, Medical Implant Communication Service (MICS), Low Power, Phase-Locked Loop (PLL).