Design of Timing-Error-Tolerant Digital Filters for Various Filter Transformations

• Main Authors: Zhi-Hong Liang, 梁志鴻
• Other Authors: Hsin-Chou Chi
• Format: Others
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/4c2ycw

碩士 === 國立東華大學 === 電機工程學系 === 102 === In modern VLSI design, especially in system-on-chip, the number of transistors in a single chip keeps increasing thanks to the advance of chip manufacturing technology. However, as the feature size of modern chips shrinks, the circuits become more and more susceptible to noise, wire delay, and soft errors. One of these main problems is timing errors which are caused by process variation, device aging, etc. Such timing error problems can cause system failures. Hence, it is an important issue to solve the timing error problem while maintaining the performance of a chip. This thesis proposes various transformation designs for VLSI digital filters for tolerating multiple timing errors. We have developed a design methodology for VLSI digital filters, which can detect and tolerate multiple timing errors on-line. In order to achieve high performance of the digital filters, different transformations for various digital filter designs are applied. According to the design requirements, we choose the appropriate transformation for the filter in order to improve the performance, while it can still tolerate multiple timing errors. We have applied our techniques to two example digital signal filter designs, including a FIR filter and an IIR filter. Four examples for each circuit are studied and evaluated. We have implemented them using cell-based design flow on TSMC manufacturing technology. The implementation results show that our designs achieve high performance and tolerance of multiple timing errors for digital filters with reasonable cost.