| Summary: | 碩士 === 國立彰化師範大學 === 電子工程學系 === 102 === In this thesis the designed circuits utilize the structure of a first-order temperature compensation bandgap voltage reference circuit, and nonlinear piecewise compensated circuits for curve compensation to generate second-order temperature compensation current. Then, using resistor ratio adjusts the value of compensation current to produce a low temperature sensitivity output reference voltage. The TSMC 0.18 µm 1P6M CMOS models are used in the circuit simulation.
When the supply voltage VDD is 1.3 V and the temperature range is from -40 ℃ to 120 ℃, the pre-layout simulation results show as follows:
1. The average value of output voltage reference is about 716.79 mV.
2. The deviation value is about 0.096 mV, and the temperature coefficient is about 0.84 ppm/℃.
3. The power consumption is about 117.73 µW, and the power supply rejection ratio (PSRR) is about 57 dB.
When the supply voltage VDD is 1.3 V and the temperature range is from -40 ℃ to 120 ℃, the post-layout simulation results show as follows:
1. The average value of output voltage reference is about 778.31 mV.
2. The deviation value is about 0.104 mV, and the temperature coefficient is about 0.85 ppm/℃.
3. The power consumption is about 148.88 µW, and the power supply rejection ratio (PSRR) is about 46 dB.
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