Chip Design of High Speed Low Power Flash ADC Based on a Digital Comparator Architecture
碩士 === 國立彰化師範大學 === 資訊工程學系 === 102 === In this thesis, we designed a 6-bit and an 8-bit flash Analog-to-Digital converter (ADC). By using a specially designed architecture of series resistors and Digital-comparators, the proposed flash ADC attains a linear distribution of switching voltages for...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/60712499325893638607 |