A 5-bit Flash ADC design with reduced comparators number

• Main Authors: He-Tian Wang, 王和田
• Other Authors: Chang-Pei Yi
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/99360664486943374462

碩士 === 國立彰化師範大學 === 資訊工程學系 === 102 === In this thesis, a new 5-bit flash analog to digital converter(ADC), with multi-input multiplexer technique, is designed. The proposed Analog to Digital Converter has low transistor count compared with conventional ADC. The advantages of the ADC are low power consumption and high speed. The ADC consists of multi-input multiplexer and six comparators. To simplify traditional circuit complexity. This thesis presents the circuit which was simulated in TSMC 1P6M 0.18u micron CMOS process. The supply voltage range from 0 to 1.8V, The circuit power consumption(Pd) is 0.725mW and the sampling frequency is about of 2GHz. The integral nonlinearity (INL) is less than 0.4LSB and the differential nonlinearity (DNL) is less than 0.06LSB. The simulation is completed by Tanner EDA tool and Hspice tool.