DSP Implementation of a Transceiver for Power Line Communications
碩士 === 國立中央大學 === 通訊工程學系在職專班 === 102 === Power Line Communications (PLC) has attracted much attention due to the wide availability of power distribution lines. PLC can transmit signal over the existing AC electrical wiring without building whole new network. In this thesis,we design and implement a...
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ndltd-TW-102NCU056501022015-10-13T23:55:41Z http://ndltd.ncl.edu.tw/handle/01808552915180709247 DSP Implementation of a Transceiver for Power Line Communications 以DSP實現電力線通訊傳收器 Chung-Hsiang Chiu 邱崇享 碩士 國立中央大學 通訊工程學系在職專班 102 Power Line Communications (PLC) has attracted much attention due to the wide availability of power distribution lines. PLC can transmit signal over the existing AC electrical wiring without building whole new network. In this thesis,we design and implement a software dened OFDM transceiver over powerline on the dsp development platform. In this platform, we use C6416 DSP Starter Kit (dsk)、FPGA and PLC Analogy-Front-End (AFE). The transmitter includes high-rate convolutional encoder, signal interleaver, constellation mapper,Invers FFT, cyclic prex inserter and preamble inserter. The receiver includes signal synchronizer, FFT, channel estimator, channel equalizer, hard decider, signal de-interleaver and channel decoder etc. Transmission bandwidth between 1:91MHz and 16:66MHz. Yih-Min Chen 陳逸民 2014 學位論文 ; thesis 83 zh-TW |
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碩士 === 國立中央大學 === 通訊工程學系在職專班 === 102 === Power Line Communications (PLC) has attracted much attention due to the wide availability of power distribution lines. PLC can transmit signal over the existing AC electrical wiring without building whole new network.
In this thesis,we design and implement a software dened OFDM transceiver over powerline on the dsp development platform. In this platform, we use C6416 DSP Starter Kit (dsk)、FPGA and PLC Analogy-Front-End (AFE). The transmitter includes high-rate convolutional encoder, signal interleaver, constellation mapper,Invers FFT, cyclic prex inserter and preamble inserter. The receiver includes signal synchronizer, FFT, channel estimator, channel equalizer, hard decider, signal de-interleaver and channel decoder etc. Transmission bandwidth between 1:91MHz and 16:66MHz.
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author2 |
Yih-Min Chen |
author_facet |
Yih-Min Chen Chung-Hsiang Chiu 邱崇享 |
author |
Chung-Hsiang Chiu 邱崇享 |
spellingShingle |
Chung-Hsiang Chiu 邱崇享 DSP Implementation of a Transceiver for Power Line Communications |
author_sort |
Chung-Hsiang Chiu |
title |
DSP Implementation of a Transceiver for Power Line Communications |
title_short |
DSP Implementation of a Transceiver for Power Line Communications |
title_full |
DSP Implementation of a Transceiver for Power Line Communications |
title_fullStr |
DSP Implementation of a Transceiver for Power Line Communications |
title_full_unstemmed |
DSP Implementation of a Transceiver for Power Line Communications |
title_sort |
dsp implementation of a transceiver for power line communications |
publishDate |
2014 |
url |
http://ndltd.ncl.edu.tw/handle/01808552915180709247 |
work_keys_str_mv |
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