| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 102 === With the increasing demand of portable electronic devices, reducing power consumption has become the major concern to increase the battery life. The demand of power management ICs are also increasing in those electronic products. Moreover, due to the fierce market competition and the need of fast time-to-market, high design yield is also one of the major objectives in industry. Therefore, an automated synthesis tool is essential to shorten the design cycles and improve the design yield.
This thesis presents an automatic synthesis tool for low dropout regulator (LDO) considering process variations and layout effects. This tool can generate the required designs from specifications to layout through a user-friendly GUI. In order to optimize the design yield with accurate variation consideration, the worst case distance (WCD) concept is integrated into the layout-aware equation-based sizing approach in this work. The device in the low dropout linear regulator and its error amplifier are both considered in the optimization process for reducing the overall circuit cost.
The proposed sizing algorithm has been implemented in Linux with the LP solver CPLEX, incorporating with an automatic layout generation tool implemented with C/C++ and Tcl/Tk on Laker. As demonstrated in the experimental results, this synthesis tool is able to achieve the required specifications in a short time and significantly improve the design yield while the post-layout performance is still guaranteed.
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