A Fast-locking Phase-locked Loop with a Digital Band Selector and an Adaptive Phase Frequency Detector
碩士 === 國立中央大學 === 電機工程學系 === 102 === In this thesis, a fast locking PLL is proposed. Its oscillator is composed of 4-stage differential delay cells and can output 8 phase, 5 GHz clock signals without using inductors.The oscillator adopts multi-band architecture to lower the gain of the voltage contr...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85980441320882082049 |