A Fast-locking Phase-locked Loop with a Digital Band Selector and an Adaptive Phase Frequency Detector

• Main Authors: Po-Yi Li, 李柏逸
• Other Authors: Kuo-Hsing Cheng
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/85980441320882082049

碩士 === 國立中央大學 === 電機工程學系 === 102 === In this thesis, a fast locking PLL is proposed. Its oscillator is composed of 4-stage differential delay cells and can output 8 phase, 5 GHz clock signals without using inductors.The oscillator adopts multi-band architecture to lower the gain of the voltage controlled oscillator, KVCO, and the band selector picks out the adequate band to lock in. The adaptive phase frequency detector speed up the intra-band tracking so that the control voltage(VC)could vary agilely and the phase difference could be eliminated rapidly. This study was implemented by TSMC 90 nm(TN90GUTM) 1P9M process with 1 V supply voltage. A 50 MHz clock is used to be input reference clock of PLL, and the output frequency is 5 GHz. The period jitter of output frequency is 10.3 ps(pk-pk). The locking time of the proposed PLL is 1.6 us at 5 GHz and the power consumption of the PLL is 10.1 mW. The chip area is 924.58 924.58 um2 and the core area is 236.23 x 313.54 um2.