A Fast CUDA-Based Static Timing Analysis (STA) Engine and Its Application

• Main Authors: Wang, Hsuan-Wei, 王鉉崴
• Other Authors: Wen, Hung-Pin
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/67677336397514540440

碩士 === 國立交通大學 === 電機工程學系 === 102 === Graphics processing unit (GPU) enables the possibility of parallel computing for Static Timing Analysis (STA). However, memory access and synchronization between cores has become more difficult in STA and thus its algorithm needs to be re-designed. In this work, we developed a CUDA-based STA engine that incorporates cell levelization and type sorting (CLTS), timing table restructuring (TTR), table indexing by texture (TIT) and hardware-accelerated rendering (HAR) for high-parallelism. Cell levelization and type sorting (CLTS) levelize cells and sort their types in order to efficiently access the same timing library. Timing table restructuring (TTR) modifies signal structure of one cell to increase the throughput. Table indexing by texture (TIT) combines the axes of each table to access data jointly while hardware-accelerated rendering (HAR) expands look-up tables (LUTs) without extrapolation. As result, our fast CUDA-based STA engine shows an average of 12.85X speedup on experimental circuits over the CPU version. The proposed work outperformed PrimeTime in speedup by three orders of magnitude.