Low Vmin Nanoscale SRAM Circuit Design

• Main Authors: Lien, Nan-Chun, 連南鈞
• Other Authors: Wu, Wen-Rong
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/96078265884322261110

博士 === 國立交通大學 === 電信工程研究所 === 102 === The Internet of Things (IoT) and wearable devices bring a more strong demand for low-power memory, even beyond the current level of demands for smartphones and tablet devices. In many low-power solutions, to reduce the operating voltage is a relatively straightforward and simple processing technique. However, with the development of deep sub-micron process technology, the variations and mismatch problems of the high density and high performance devices become more and more significant and the optimization of the design parameters are under the major consideration. This also strictly limits the voltage operating range of static random access memory. With the industry production static random access memory, there is no promise to access the memory under a stable circumstance at a lower voltage operation so far. In this thesis, we propose four auxiliary circuits to strengthen the stability of static random access memory at lower operation voltage. In addition, we also propose new solutions for the low VMIN improvement with the new 8T structure static random access memory. Finally, a novel operation scheme to improve the VMIN value is provided for the conventional dual-port static random access memory applications.