| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 102 === This thesis discusses two circuit designs. One is a wideband CMOS receiver, and the other is a RF-to-digital converter.
The 0.18um-CMOS, 17-26 GHz (K-band) receiver contains RF LNA, wideband mixer, IF amplifier, and LO frequency doubler. The circuit architecture, simulation results, chip layout and measured results are presented. The conversion gain of mixer is 0 dB. The IF-RF isolation is 40 dB.
The RF-to-digital converter consists of sample-and-hold circuit, preamplifier, comparator, and encoder. The circuit architecture, simulation results and 90nm-CMOS and 0.18-CMOS layouts are discussed.
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