| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 102 === The improvement in the semiconductor technology seems unable to maintain the
Moore’s law. Therefore, three-dimensional (3-D) IC is imported to extend this limit.
3-D IC is to stack several 2-D ICs and use through silicon via (TSV) as iter-layer connection. In this thesis, a timing-driven 3-D floorplanner is proposed, and a two-stage timing analysis method is applied to estimate circuit delay. In the first stage, a simple yet efficient look-up table method is adopted, while an accurate timing analysis algorithm is used in second stage. The proposed method can provide a reliable floorplanning result for later steps in physical design flow. Comparing with traditional min-wirelength floorplanner, the proposed algorithm can improve timing slack a lot.
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