| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 102 === In this thesis, a novel wide band low noise amplifier combined negative resistance with common gate structure for LTE applications are presented. The research focused on how to reduce the power consumption and noise figure, and using negative resistance to achieve the effect of input impedance matching. In the past, the design of low-noise amplifier used RLC feedback or lengthy inductance, capacitance in series and parallel to achieve broadband matching circuit at the input, however our circuit used fewer of components to increase the bandwidth. In our design, a common gate amplifier with negative resistance using the frequency independent of the transistor current is to replace the traditional architecture of passive inductor at input, and with the gm-boost technique to achieve low power and noise reduction effectively. The shunt peaking network at drain is drawn to further suppress the high-frequency noise and a low noise level is achieved. The proposed LNA is implemented by the TSMC 0.18-μm CMOS technology process, and measured by use of CIC instruments.
The measured results are as follows: bandwidth of 0.5 ~ 3.7 GHz, input and output reflection loss are greater than -12 dB, the maximum power gain is 17.8 dB, the minimum noise figure is 3.3 dB, at 2.7 GHz, the P1dB gain compression point is -20 dBm, the IIP3 cut-off point is -10.3 dBm, the core circuit power consumption is 6.48 mW, and the overall layout area including the pads is 0.716 * 0.744 = 0.533 mm2.
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