| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 102 === As the advancement of VLSI technology, power grid analysis becomes a challenging task because of numerous amounts of power grid nodes on a chip. Typically, power network needs to be frequently verified during the design, and violations often occur while the chip is acting. Therefore, an effective method that is able to capture the transient behavior of modified power network is highly needed for designers. This work integrates macro modeling techniques, sparse recovery mechanisms (orthogonal matching pursuit), continuous characteristic of transient analysis, and a proposed adaptive error control system to develop an efficient and reliable RLC power grid transient incremental analyzer. The developed analyzer not only can deal with the change of existing element values but also can handle the modification of topology. Compared with redoing transient analysis by using the macro modeling technique, the developed incremental analyzer can achieve orders of magnitude speedup with negligible loss of accuracy.
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