Scheduling Algorithms of Co-optimizing Thread-Level- Parallelism and Cache Utilization for GPGPUs 研
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Thread-Level-Parallelism (TLP) and cache utilization are two significant performance factors of modern throughput processors. The conflicting correlation between the two factors has made the design a non-trivial task. Increasing TLP would aggravate cache co...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2014
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/99321023691038445807 |