An OFDM Baseband Processor Design for Body Channel Communication

• Main Authors: Chang, Jen-Shin, 張紝炘
• Other Authors: Lee, Chen-Yi
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/65633104700296480931

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Recently, a new technique - body channel communication (BCC) emerges to extend the field of application, and is already included in standard IEEE 802.15.6. In BCC, a simple touch can be used to enable the transmission such that it can be applied to multimedia transmission application, payment system or entry access control system to improve convenience in our daily life. Recent work about BCC in the literature has data rate up to 10 Mbps which is not allowable for multimedia transmission application. To support that, OFDM modulation technique is adopted with high data rate and high spectral efficiency for band-limited BCC channel. To develop an OFDM baseband system for BCC, the measurement of transmission schemes influencing the channel is conducted. In our environment settings, the capacitive coupling approach is more suitable in the transmission distance on a single person and the proper transmission band is 30 – 50 MHz. By reducing the external wireless interference and the instrumental noise, a body channel impulse response is built with respect to 3 transmission distances on the body for the system simulation. In baseband processing, due to the character of BCC channel, high accuracy time domain equalizer is applied with little overhead of hardware complexity to enhance transmission reliability. And Zad-off Chu sequence is selected accompanied with ZFS detection scheme to combat noisy environment about body antenna effect. To verify the baseband processor design, the BCC prototype composed of FPGA and PCB is built for real transmission on human body. With proposed baseband processor design, there are over 9 percentage point enhancement and 98% detection rate in average, and BER performance is also improved in 0.3 order. And the operating speed of the prototype is limited by imperfection of the analog components, but it is still achieved that 10-2 BER performance in 13 Mbps throughput rate. In the chip implementation, the proposed BCC processor could reach 29.1 Mbps data rate, which is the highest one compared to state-of-the-art. With low power technique such as voltage scaling and clock gating, the energy per bit performance is also comparable.