Statistical Study and Rapid Prediction Methodology of RRAM SET Speed-Disturb Dilemma

• Main Authors: Luo, Wun-Cheng, 羅文呈
• Other Authors: Hou, Tuo-Hung
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/47197877804646972569

博士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Resistive-switching random access memory (RRAM) has the potential to become the front runner for future nonvolatile memory because of its simple structure, low operating voltage, and excellent scalability. To fulfill the requirement of nonvolatile memory application, the tradeoff between desired high SET speed and disturb immunity has to be carefully engineered using a highly nonlinear voltage-time (V-t) dependence at SET. This is also known as the SET speed-disturb dilemma. However, most studies have not considered the random variation effect of SET time (tSET) on the SET speed-disturb dilemma. The tSET variation is distributed across several orders of time, causing the unacceptable error in predicting the SET speed-disturb properties. Therefore, a statistical methodology for predicting the SET speed-disturb dilemma by considering the variation effect is needed. Firstly, we propose an analytical percolation model of tSET statistics, which is also based on the oxide breakdown theory. The model provides a thorough explanation of the stochastic nature of the tSET variation and voltage dependence of the experimental data. Furthermore, the validation of the percolation model was first performed on the SET variation of two distinct RRAM devices, Ti/TiO2/Pt based on oxygen-vacancy filament resistive switching (RS) and Ni/HfO2/Si based on metal filament RS. The power-law V-t dependence was also first verified across ten orders of magnitude in time using constant voltage stress (CVS). Then based on the Weibull distribution and voltage acceleration relation, we present a statistical projection procedure for SET speed-disturb properties using constant voltage stress (CVS). However, the conventional CVS testing requires substantial time. We demonstrated that the essential parameters of the Weibull distribution and voltage acceleration relation measured by time-consuming CVS testing can be extracted directly using a ramped voltage stress (RVS) testing, and then proposes a rapid prediction method based on RVS to reduce the time and cost of reliability testing. Furthermore, a device design guideline for the desired SET speed-disturb properties is discussed. Finally, because of the rich RVS data available in the literature, the current status of RRAM technology in meeting the strict requirement of the SET speed-disturb dilemma was discussed. This work performed comprehensive analyses of the SET speed-disturb dilemma of RRAM by considering statistical SET variation. The theoretical framework, testing methodology, device design guideline, and present status of RRAM technology are discussed. We believe that our research provides a useful design guideline and testing methodology for future RRAM researches.