| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Highly integrated and miniaturized neural sensing microsystems are crucial for brain function investigation and neural prostheses realization for capturing accurate signals from an untethered subject in his natural habitat. In high-density neural sensing microsystems, a 16-channel configurable lifting-based DWT is proposed for extracting the features of EEG/ECoG signals by filtering the neural signal into different frequency bands. Based on the lifting-based DWT algorithm, the area and power consumption can be reduced by decreasing the computation circuits. Additionally, both the time window and mother wavelets can be adjusted. Moreover, the power-gating and clock-gating techniques are utilized to further reduce the energy consumption for the energy-limited bio-systems.
The four proposed configurable 4-chanel DWTs are designed and implemented using TSMC 65nm CMOS Low power process with total area of 0.11 mm2 and power consumption of 26 µW. Moreover, this proposed DWT is also implemented in Lattice MachXO2-1200 FPGA and integrated in a high-density neural-sensing microsystem in 2.5D heterogeneous integration with power consumption of 211.2 µW.
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