An ultra-low voltage time-based delta-sigma analog-to-digital converter
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === This thesis presents an ultra-low voltage time-based delta-sigma analog-to-digital converter. The bandwidth, sampling clock, supply voltage and ENOB of this converter are 2MHz, 250MHz, 0.3V~0.44V and 6.6 ~ 8.4 bits respectively. The ADC uses a 2nd order con...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21791299202795227924 |