An ESD aware Floorplan Algorithm with Efficient CDM Estimation for Multiple Power Domain Designs
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === The issue on reliability of the device becomes more critical as transistor progressively scales down. Smaller transistor and hence thinner gate oxide implies transistors are more vulnerable against an Electrostatic Discharge (ESD) event. Among the three mod...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72396408531251287028 |