| Summary: | 碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === The issue on reliability of the device becomes more critical as transistor progressively scales down. Smaller transistor and hence thinner gate oxide implies transistors are more vulnerable against an Electrostatic Discharge (ESD) event. Among the three models in ESD, Charged Device Model (CDM) has the greater potential to deal catastrophic damage to the device due to its faster and larger discharging current. Damage induced from the other two ESD models, human body model (HBM) and machine model (MM) can be effectively protected at device stage. However, protection against a CDM event is much more sophisticated due to its unpredictability. While most previous works on ESD protection methodology are implemented at device stage, we propose an efficient and effective methodology to protect against a CDM event at design stage. When floorplan of a design is determined, we propose a power clamp placement algorithm derived from clustering analysis to place power clamp at strategic location which can effectively minimize number of power clamps while achieving better protection compared to conventional method.
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