A 2.56 Gb/s Non-binary LDPC Decoder Architecture using Trellis Min-Max Algorithm

• Main Authors: Lin, Rih-Hio, 林日和
• Other Authors: Chang, Hsie-Chia
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/72832298453742748110

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Non-binary LDPC codes extended from binary LDPC codes have excellent decoding performance and high burst error resistance, and they have lower routing complexity in contrast to binary LDPC codes. However, the challenges are the high computational complexity and huge memory usage for VLSI implementation. In this thesis, a hardware and energy efficient architecture for implementing non-binary LDPC decoder using Improved Trellis Min-Max algorithm is presented. The Improved Trellis Min-Max algorithm has low computational complexity due to it easily hardware sharing, and we significantly enhance the throughput by eliminating the redundant cycles. Benefited by layered scheduling and appropriate code construction, storage elements of the edge message are reduced as well. Furthermore, a stall-free pipeline architecture is proposed to achieve high throughput. Using 90-nm CMOS process technology, a (2,4)-regular non-binary quasi-cyclic (QC) LDPC decoder over GF(32) is implemented with 1063k decoder gate count, while the chip area including testing consideration is 2.29 × 2.56 mm2. From the post-layout simulation results, the decoder throughput can achieve over 2.5 Gbps with 817 mW under 333 MHz clock frequency and bit error rate 10−6. Compared with state-of-the-art designs, this work has not only the best decoding performance but also over 7 times improvement in both hardware efficiency and energy efficiency.