A 2.56 Gb/s Non-binary LDPC Decoder Architecture using Trellis Min-Max Algorithm
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === Non-binary LDPC codes extended from binary LDPC codes have excellent decoding performance and high burst error resistance, and they have lower routing complexity in contrast to binary LDPC codes. However, the challenges are the high computational complexity...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/72832298453742748110 |