Design of Low Power Successive Approximation Register Analog-to-Digital Converter

• Main Authors: Lee, Mao-Cheng, 李茂誠
• Other Authors: Hu, Shu-I
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/91556839843235408859

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === To date ADCs play essential roles in the communication fields and in the bio-sensor applications. High-speed and low-power Analog-to-Digital converters (ADCs) are required in these applications. However, with the development of the CMOS technology, the design of high quality analog circuits becomes a challenge. The Successive approximation Register (SAR) architectures primarily consist of digital circuits. With this property, the SAR ADCs are more suitable fabricated in advanced CMOS technology than other structures. In this thesis, we present two SAR ADC architectures: a R-2R ladder DAC and a binary capacitive DAC. For the high speed applications, we chose a R-2R resistive DAC in our first work. We design a 10-bit R-2R ladder SAR ADC in TSMC 65nm CMOS technology. In addition, for the high resolution applications, we design a 12-bit capacitive SAR ADC in TSMC 65nm CMOS technology and we introduce two digital calibration technologies in this work.