Study and Design of Predictive Digital Current Controlled Buck Converter

• Main Authors: Yung-ChienChang, 張永謙
• Other Authors: Chien-Hung Tsai
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/99355531979426880731

碩士 === 國立成功大學 === 電機工程學系 === 102 === In this thesis, a predictive digital current mode controlled buck converter is presented. Unlike traditional digital current mode control which needs to sample the rapidly-changed inductor current information with high frequency and resolution ADC. The frequency in this structure is as low as switching frequcncy. Furthermore, it can be implemented with low resolution to reduce cost and power consumption. Theoretically, predictive current mode control loop let the inductor current track the current command with one cycle delay, the system delay resulted from ADC conversion and compensator calculation would cause the current-loop response to become slower and thus have worse transient performance. In order to improve the current-loop response to reach one-cycle delay, this work proposes a duty calibration technique for predictive digital average current mode controlled buck converter. Experimental results from FPGA prove that the technique for one-cycle delay is feasible and improving the transient performance. Besides, the earlier developed compensator design automation GUI(Graphical User Interface) tool for digital voltage mode is extended to predictive current mode structure, simplifing complicated compensator design flow and reducing the time-to-implementation.