Breakdown Voltage and Reliability Studies of Devices in NAND Flash Memory Periphery Circuitry

• Main Authors: Chun-PoChang, 張鈞博
• Other Authors: Jone-Fang Chen
• Format: Others
• Language: en_US
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/58759552904041180838

碩士 === 國立成功大學 === 微電子工程研究所 === 102 === In this thesis, we study the high-voltage device which is depletion-mode lateral diffused metal-oxide-semiconductor (LDMOS). The HV device in the periphery circuit is applied to NAND Flash Cell for Program/Erase operation. In periphery circuit, the high off-state breakdown voltage (off-state VBD) is an important requirement for this device. Therefore, the LDMOS breakdown mechanism with different BF2 implant by varying implant dosage in N- region is investigated. As expected, the off-state breakdown voltage increase with the raise of BF2 concentration. Experimental data and technology computer aided design simulations show that gate-induced-drain-leakage (GIDL) and PN junction breakdown are responsible for the variation of breakdown voltage. Moreover, in the circuit operating environment, there might be hot carrier degradation in the device. The damage will happen while device is programming or erasing data. Generally, the ISUB peak will be the index of the HCI degradation. However, in our study, the measurement results contradict pervious study because the distribution of the impact ionization peak would dominant the hot carrier degradation instead of the amount of the ISUB current. The impact ionization which is located near drain side is greater with higher BF2 concentration. In conclusion, the device with higher BF2 implant suffers worse HCI degradation because of more high energy carrier injection. According to the results in this study, care should be taken when we implant the BF2 into the drift region, since there is a trade-off between VBD and HCI reliability issue.