| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 102 === Recently, energy-limited applications such as wireless sensing devices of portable or wearable, mobile products, etc., require high-efficient ADCs to extend the battery life of these devices. With the technology downscaling, low-voltage ADCs are required for implementation of low supply SoC design. SAR ADCs are suitable for these applications due to their excellent power efficiency and low-voltage potential compared to other ADCs architectures (e.g., pipelined ADC).
This work presents a low-voltage and energy-efficient 10-bit SAR ADC with two techniques. The proposed charge sharing switching (CSS) method can reduce the switching power by reusing the energy stored in CDAC without the deteriorated linearity problem in conventional charge sharing SAR ADC. Meanwhile, decreasing the supply voltage is helpful in reducing the power dissipation of SAR ADC. However, low supply voltage may deteriorate the signal-to-noise ratio (SNR) due to small signal power and poor accuracy of the comparator. A flexible comparator with time-based window function is proposed to achieve fast comparison as well as low-noise requirements with small power dissipation. The flexible comparator with time-based window function can alleviate the comparison error without penalty of huge power consumption. Furthermore, the time-based window function can minimize the conversion error induced by insufficient DAC settling time and improve the ADC linearity by skipping unnecessary capacitor switching.
The proposed 10-bit SAR ADC operates at 100kS/s with 0.4V supply voltage in 90nm CMOS process. The measurement results show that the prototype ADC achieves 8.89 effective number of bit (ENOB) with Nyquist rate input and consumes only 107nW. The figure-of-merit (FOM) is 2.23fJ/conversion-step. The active area (excluding output buffers) of the prototype ADC is 175μm x 110μm.
|
|---|
