| Summary: | 碩士 === 國立勤益科技大學 === 電子工程系 === 102 === A rapid oscillator design approach is proposed in this thesis. By using the rapid oscillator design approach, three CMOS Quadrature Voltage Controlled Oscillator (QVCO) are proposed, and to compare with five previous works. Based on TSMC CMOS 1P6M 0.18um standard process technology with supply voltage 1.8V, Spectre-RF and HSPICE are used to perform simulation on five previous QVCOs and three proposed QVCOs. Proposed Type-Ⅰ, Type-Ⅱ and Type-Ⅲ QVCO schemes have significantly decreased phase noise (Pnoise), which are -167.05 dBc/Hz, -172.84 dBc/Hz and 177.94 dBc/Hz at 1 MHz offset frequency, respectively. Type-Ⅲ has the best FoM (Figure of Merit) to be -227.46 dBc/Hz. The oscillation frequency of QVCO schemes has ranging from 750MHz to 1.15GHz as the control voltage adjusted from 0V to 1.8V.
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