Investigation of defects of election-plating of Cu onto silicon hole substrate
碩士 === 國立勤益科技大學 === 化工與材料工程系 === 102 === Plating process of silicon substrate is a very important process and link for die stacking module。Small and beautiful appearance of the consumer market demand for electronic products and Semiconductor processing capability, fine pitch ability more go down， th...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/27668180159184599170 |
| Summary: | 碩士 === 國立勤益科技大學 === 化工與材料工程系 === 102 === Plating process of silicon substrate is a very important process and link for die stacking module。Small and beautiful appearance of the consumer market demand for electronic products and Semiconductor processing capability, fine pitch ability more go down， the process more difficult. depend on these requirement. Chip stacking technology bring about。
This plating line is mainly use for conducting line，The current research for high aspect ratio via plating capability and plating defects become more and more important. it will impact product function and reliability。In other words，impact product life-time。Ideal via re-filling ability，the final plating result will without some defects, like as in-complete filling、void、over-burden。This article is explore the relationship between the plating machine factor for poor quality of the plating。
|
|---|