An 11-bit single-ended inverter-based successive approximation analog to digital converter for low power and ESD design

• Main Authors: Guan-Wei Jeng, 鄭冠偉
• Other Authors: Wei-Liang Lin
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/04785883289646723693

碩士 === 國立中興大學 === 電機工程學系所 === 102 === By the progression of technology, the size of CMOS devices have been reduced constantly, which effectively shrinks the area of chip and let the standard of Analog to Digital Converters have completely new development, a low speed ADC can be widely used in Biomedical Systems and portable electronics products, the appearance of many electronic products have became light, thin, short and small so that we find the quantity of electric charge is limited, and that’s why we have to design a low power consumption circuit to improve this problem. In addition, our laboratory had used the process by 90nm to carry out high-speed analog to digital converters in last two years, the device size in advancing process is smaller than others, and gate oxide layer tends to suffer from external Electrostatic damage such as HBM and MM, as a result, we start to construct ESD protection circuit in order to protecting Internal circuit from Electrostatic damage. This essay realizes a Analog to Digital Converters, the process used TSMC 0.35μm CMOS Technology, the resolution of 11 bits, the framework for the successive approximation analog to digital converter, the goal of this designation is to reduce the power consumption, which mainly improve comparator and capacitor array’s switch consumption, comparator used inverter-based, Taking capacitor array and switch apart A-side and B-side, we can carry out the first comparison without switching any after sampling phase, In addition let sample and hold circuit used Bootstrapped switch can improve the decrease SNDR range when Input frequency closes Nyquist Rate. In Supply voltage is 1.2V、Input Frequency is 1.64kHz、VPP is 3V、Sampling frequency is 25kS/s；the result of the survey is that DNL is 0.88/-0.90 LSB、INL is 0.72/-1.14 LSB、SNDR is 63.76 dB、SFDR is 73.99dB、ENOB is 10.28bit、power consumption is 3.37μW、FOM is 181 fJ/Conv.-setp、chip area is 1.41mm2（exclusive of PAD）.In ESD protection circuit, the process is TSMC 0.18μm CMOS Technology, and in the mode of HBM, the endurance capacity of input pin is about ±150V, and the endurance capacity of output pin is about ±450V.