A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure

碩士 === 國立中興大學 === 電機工程學系所 === 102 === This thesis describes two differential high-speed asynchronous successive approximation analog to digital converters, compared to the single-ended successive approximation analog-to-digital converter, the differentia structure can improve the sampling frequency...

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Main Authors: Shih-Ying Tseng, 曾世穎
Other Authors: 林維亮
Format: Others
Language:zh-TW
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/29325643947363123037
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spelling ndltd-TW-102NCHU54410122017-06-25T04:37:52Z http://ndltd.ncl.edu.tw/handle/29325643947363123037 A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure 雙端輸入之高速非同步連續逼近式類比數位轉換器使用單一電容切換程序 Shih-Ying Tseng 曾世穎 碩士 國立中興大學 電機工程學系所 102 This thesis describes two differential high-speed asynchronous successive approximation analog to digital converters, compared to the single-ended successive approximation analog-to-digital converter, the differentia structure can improve the sampling frequency of the analog-to-digital converter. In addition, the design can effectively enhance the sampling frequency by reduce the delay time of the critical path in digital control logic circuit. With TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process, the sampling frequencies are, respectively, 66M Sample / s and 166M Sample / s. TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.556 mm2 with sarf2_12_decouple chip (10 bits) .The supply voltage is 1.2V, the sampling frequency is 66MS / s, input sine wave frequency is 10MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 6.86. Input sine wave frequency is 100kHz, the measured differential nonlinearity ranged between -1LSB~5.25LSB, integral nonlinearity ranged between -5.20LSB~3.16LSB, the total power consumption is 4.78mW ,FOM is 0.624pJ / Conversion-step. TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.520 mm2 with sarf2_31_decouple chip (8 bits) .The supply voltage is 1.2V & 1.4V, the sampling frequency is 166MS / s, input sine wave frequency is 20MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 5.67. Input sine wave frequency is 200kHz, the measured differential nonlinearity ranged between -1LSB~2.07LSB, integral nonlinearity ranged between -0.76LSB~3.76LSB, the total power consumption is 11.58mW ,FOM is 3.3pJ / Conversion-step. 林維亮 2013 學位論文 ; thesis 93 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立中興大學 === 電機工程學系所 === 102 === This thesis describes two differential high-speed asynchronous successive approximation analog to digital converters, compared to the single-ended successive approximation analog-to-digital converter, the differentia structure can improve the sampling frequency of the analog-to-digital converter. In addition, the design can effectively enhance the sampling frequency by reduce the delay time of the critical path in digital control logic circuit. With TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process, the sampling frequencies are, respectively, 66M Sample / s and 166M Sample / s. TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.556 mm2 with sarf2_12_decouple chip (10 bits) .The supply voltage is 1.2V, the sampling frequency is 66MS / s, input sine wave frequency is 10MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 6.86. Input sine wave frequency is 100kHz, the measured differential nonlinearity ranged between -1LSB~5.25LSB, integral nonlinearity ranged between -5.20LSB~3.16LSB, the total power consumption is 4.78mW ,FOM is 0.624pJ / Conversion-step. TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.520 mm2 with sarf2_31_decouple chip (8 bits) .The supply voltage is 1.2V & 1.4V, the sampling frequency is 166MS / s, input sine wave frequency is 20MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 5.67. Input sine wave frequency is 200kHz, the measured differential nonlinearity ranged between -1LSB~2.07LSB, integral nonlinearity ranged between -0.76LSB~3.76LSB, the total power consumption is 11.58mW ,FOM is 3.3pJ / Conversion-step.
author2 林維亮
author_facet 林維亮
Shih-Ying Tseng
曾世穎
author Shih-Ying Tseng
曾世穎
spellingShingle Shih-Ying Tseng
曾世穎
A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure
author_sort Shih-Ying Tseng
title A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure
title_short A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure
title_full A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure
title_fullStr A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure
title_full_unstemmed A Differential High Speed Asynchronous Successive Approximation Register ADC With Monotonic Capacitor Switching Procedure
title_sort differential high speed asynchronous successive approximation register adc with monotonic capacitor switching procedure
publishDate 2013
url http://ndltd.ncl.edu.tw/handle/29325643947363123037
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