| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 102 === This thesis describes two differential high-speed asynchronous successive approximation analog to digital converters, compared to the single-ended successive approximation analog-to-digital converter, the differentia structure can improve the sampling frequency of the analog-to-digital converter. In addition, the design can effectively enhance the sampling frequency by reduce the delay time of the critical path in digital control logic circuit. With TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process, the sampling frequencies are, respectively, 66M Sample / s and 166M Sample / s.
TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.556 mm2 with sarf2_12_decouple chip (10 bits) .The supply voltage is 1.2V, the sampling frequency is 66MS / s, input sine wave frequency is 10MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 6.86. Input sine wave frequency is 100kHz, the measured differential nonlinearity ranged between -1LSB~5.25LSB, integral nonlinearity ranged between -5.20LSB~3.16LSB, the total power consumption is 4.78mW ,FOM is 0.624pJ / Conversion-step.
TSMC 90 nm CMOS Mixed Signal RF Low Power Standard Process LowK Cu 1P9M 1.2V process produces a chip area -- 0.921*0.520 mm2 with sarf2_31_decouple chip (8 bits) .The supply voltage is 1.2V & 1.4V, the sampling frequency is 166MS / s, input sine wave frequency is 20MHz (amplitude is 0.2V-1.0V), and measured the effective number of bits is 5.67. Input sine wave frequency is 200kHz, the measured differential nonlinearity ranged between -1LSB~2.07LSB, integral nonlinearity ranged between -0.76LSB~3.76LSB, the total power consumption is 11.58mW ,FOM is 3.3pJ / Conversion-step.
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