Design for testability to digitize capacitor and resistor mismatch of analog circuit

• Main Authors: Wei-Cheng Tai, 戴瑋呈
• Other Authors: Hsin-Wen Ting
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/zu956q

碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 102 === Recently, the System-on-Chip (SoC) are more interests in integrated circuit by researchers owing to the rapid development of integrated circuit manufacturing technology. The testing of integrated circuit is more difficult than before, and the cost of reliability tests have increased drastically. Therefore, design for testing (DFT) has become a popular topic to decrease the cost of reliability tests. The testing of integrated circuit has shifted from the back end to the fore end gradually. The thesis proposes a simple of circuit structure to measure the ratio of capacitors and resistors. A basic sigma-delta analog to digital converter and dual-slope one are integrated to realize the proposed structure. Basic circuit those can be easily design are adopted. So the proposed structure can be incorporated with other circuitry. The design in implemental in a 0.18-µm technology to verify it function.