| Summary: | 碩士 === 國立高雄應用科技大學 === 電子工程系碩士班 === 102 === High frequency, high speed and low power are the trend of electronic products. Power integrity and signal integrity have received much attention. In this paper, quad flat package (QFP) design optimization for power delivery network and signal integrity analysis is investigated. We survey the performance differences for different power ring and ground ring, different bonding diagram, different plating copper path and thickness. For the verification of power integrity, we extract and analyze the equivalent LC model of power delivery network. To verify the signal integrity, we input pseudo random binary sequence signal source to SDRAM DDR3 IBIS model and observe the performance improvement from the eye diagram.
From the eye diagram analysis result of SDRAM DDR3, it shows that the new proposed QFP design has the improved parasitic effects and less signal loss. So some products using BGA package can be packaged by QFP to reduce the cost.
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