FPGA Implementation of Physical Layer and Functional Verification of Link Layer of Universal Serial Bus

FPGA Implementation of Physical Layer and Functional Verification of Link Layer of Universal Serial Bus

碩士 === 義守大學 === 電子工程學系 === 101

Bibliographic Details
Main Authors:	Ya-Hui Tseng, 曾雅惠
Other Authors:	Yu-Jung Huang
Format:	Others
Language:	zh-TW
Published:	2013
Online Access:	http://ndltd.ncl.edu.tw/handle/10252614811215708520

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