| Summary: | 碩士 === 輔仁大學 === 電機工程學系碩士班 === 102 === In this thesis, a beamformer circuit is proposed for the high ultrasonic imaging system and implemented with integrated circuits. The beamformer circuit was consisted of a beamformer delay line(BDL) and all digital delay lock loop(ADDLL),and used these two blocks to generate the delay time for the high frequency ultrasonic imaging system in different focus distances. This thesis implemented it with integrated circuits and simulated the circuit under TSMC 0.18μm process. The delay cells of beamformer delay line can generate the delay time between 395ps and 1043ps. The highest resolution of the proposed DCDL can reach lower than 20ps besides the delay range can provide the requirements of delay time when the ultrasound focus at 5mm,7.5mm and 10mm In order to solved the problem that the poor resolution of the beamformer circuit was implemented with FPGA.
This thesis utilized the matlab FieldⅡ to obtain the ideal delay time when the high frequency ultrasonic imaging system focus powerfully. The quality of focusing can measure with resolution. The resolution of focus points at 5mm,7.5mm,10mm which was inserted the ideal delay time for beamformer will produced 0.0352mm,0.0352mm and 0.0558mm respectively. When the ultrasound imaging system used the propose beamformer, the resolution of focus points at 5mm,7.5mm,10mm was 0.0392mm,0.0434mm and 0.06mm respectively.
The proposed delay line was controlled with digital code that can solve the unstable problem of the conventional voltage controlled delay line when technology scales down. Finally the proposed beamformer not only can provide high resolution but also can generate the wide delay range for high frequency ultrasonic imaging system.
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