| Summary: | 碩士 === 逢甲大學 === 電子工程學系 === 102 === With the increasing demand of portable devices, how to use the battery energy efficiently is the most concerned problem. Small size and low power consumption requirements of the power system have become the notable points of this subject. For power management system, low-dropout (LDO) liner regulator is the most common block due to its simplicity, low noise and low power consumption characteristics. However, the conventional LDO often can not simultaneously achieve low power consumption and good transient response for the system. Therefore, a self-tuned dual pass-transistor technique and output voltage detector for capacitorless LDO to having low power consumption and good transient response is proposed in this study. The proposed LDO is designed and simulated by using tsmc 0.18μm 1P6M CMOS process. The measured results show that the proposed circuit consumes a quiescent current of 7μA at no load, and regulates the output at 1.8V from a voltage supply range of 2V to 5V. The settling time is about 7μs in transient response. Total power dissipation is 14.45μW, and the chip area is 1.1×1.1mm2.
Key words：low dropout voltage(LDO) linear regulator, capacitorless, seif-tuned dual pass-transistor, voltage detector
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