VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver
碩士 === 中原大學 === 電子工程研究所 === 102 === The purpose of this thesis is to develop a phase-locked loop frequency correction chip. This chip is composed by analog integrated circuits and digital integrated circuits. This thesis has completed digital integrated circuit part - phase-locked loop frequency cal...
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ndltd-TW-102CYCU54280372016-03-11T04:13:03Z http://ndltd.ncl.edu.tw/handle/10141964404362212420 VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver 應用於振盪電路之非同步數位介面與可程式燒錄收發器積體電路設計 Ming-Chun Tuan 段閔鈞 碩士 中原大學 電子工程研究所 102 The purpose of this thesis is to develop a phase-locked loop frequency correction chip. This chip is composed by analog integrated circuits and digital integrated circuits. This thesis has completed digital integrated circuit part - phase-locked loop frequency calibration algorithm (storage the analog parameter), phase-locked loop frequency calibration system (receive external commands to reach “trim value” and change the function of the chip), asynchronous interface design (operating frequency different between chip and programmable transceiver), minimization of the number of input / output pad (three wires of serial peripheral interface) and a programmable logic array verification system development This thesis develops phase-locked loop diagram of the product architecture. Moreover, the digital programmable transceiver will be designed to serial transmission mode with the FPGA development board. The FPGA was designed by the hardware description language. By this design, the transceiver uses this serial transmission with the boost technology to communicate with chip and then use an oscilloscope and logic analyzer to verify the correctness of the system Shih-Lun Chen 陳世綸 2014 學位論文 ; thesis 60 en_US |
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碩士 === 中原大學 === 電子工程研究所 === 102 === The purpose of this thesis is to develop a phase-locked loop frequency correction chip. This chip is composed by analog integrated circuits and digital integrated circuits. This thesis has completed digital integrated circuit part - phase-locked loop frequency calibration algorithm (storage the analog parameter), phase-locked loop frequency calibration system (receive external commands to reach “trim value” and change the function of the chip), asynchronous interface design (operating frequency different between chip and programmable transceiver), minimization of the number of input / output pad (three wires of serial peripheral interface) and a programmable logic array verification system development
This thesis develops phase-locked loop diagram of the product architecture. Moreover, the digital programmable transceiver will be designed to serial transmission mode with the FPGA development board. The FPGA was designed by the hardware description language. By this design, the transceiver uses this serial transmission with the boost technology to communicate with chip and then use an oscilloscope and logic analyzer to verify the correctness of the system
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Shih-Lun Chen |
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Shih-Lun Chen Ming-Chun Tuan 段閔鈞 |
author |
Ming-Chun Tuan 段閔鈞 |
spellingShingle |
Ming-Chun Tuan 段閔鈞 VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver |
author_sort |
Ming-Chun Tuan |
title |
VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver |
title_short |
VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver |
title_full |
VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver |
title_fullStr |
VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver |
title_full_unstemmed |
VLSI Implementation of an Asynchronous Interface Design and a Programmable Transceiver |
title_sort |
vlsi implementation of an asynchronous interface design and a programmable transceiver |
publishDate |
2014 |
url |
http://ndltd.ncl.edu.tw/handle/10141964404362212420 |
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