| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 102 === The purpose of this thesis is to develop a phase-locked loop frequency correction chip. This chip is composed by analog integrated circuits and digital integrated circuits. This thesis has completed digital integrated circuit part - phase-locked loop frequency calibration algorithm (storage the analog parameter), phase-locked loop frequency calibration system (receive external commands to reach “trim value” and change the function of the chip), asynchronous interface design (operating frequency different between chip and programmable transceiver), minimization of the number of input / output pad (three wires of serial peripheral interface) and a programmable logic array verification system development
This thesis develops phase-locked loop diagram of the product architecture. Moreover, the digital programmable transceiver will be designed to serial transmission mode with the FPGA development board. The FPGA was designed by the hardware description language. By this design, the transceiver uses this serial transmission with the boost technology to communicate with chip and then use an oscilloscope and logic analyzer to verify the correctness of the system
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