Obstacle-Aware Substrate Routing

碩士 === 中華大學 === 資訊工程學系碩士班 === 102 === Due to the limit of a single routing layer and the existence of inevitable obstacles in flip-chip and PCB designs, single-layer obstacle-aware routing becomes an important issue in RDL routing and bus routing. In this paper, based on the construction of routabil...

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Bibliographic Details
Main Authors: Chih-Wei Hsu, 許智偉
Other Authors: Jin-Tai Yan
Format: Others
Language:zh-TW
Published: 2014
Online Access:http://ndltd.ncl.edu.tw/handle/89425834793757155317
Description
Summary:碩士 === 中華大學 === 資訊工程學系碩士班 === 102 === Due to the limit of a single routing layer and the existence of inevitable obstacles in flip-chip and PCB designs, single-layer obstacle-aware routing becomes an important issue in RDL routing and bus routing. In this paper, based on the construction of routability-driven constrained Delaunay triangulation for the terminals of the given nets, the corner of the given rectangular obstacles and the corners of a routing plane, an efficient flow-based approach is proposes for single-layer obstacle-aware routing. By using single-layer obstacle-aware routing with application to pre-assignment RDL routing in flip-chip designs and bus routing in PCB designs with the inevitable rectangular obstacles, the experimental results show that our proposed flow-based approach can successfully route all the given nets in a single- layer for the tested examples in reasonable CPU time.