Design and Analysis of near threshold voltage CMOS circuits with low delay variance

Design and Analysis of near threshold voltage CMOS circuits with low delay variance

碩士 === 長庚大學 === 電機工程學系 === 102

Bibliographic Details
Main Authors:	Yung Sheng Chen, 陳永勝
Other Authors:	I. C. Wey
Format:	Others
Published:	2014
Online Access:	http://ndltd.ncl.edu.tw/handle/95477606681769063708

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