| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 102 === In the thesis, two V-band variable-gain (VGA) amplifiers with low noise and low phase variation and a single-channel beamforming receiver were developed with CMOS 90 nm process. The first VGA consists of three stages of cascoded variable gain amplifier, where two stages of current-steering were used for gain control. To reduce the noise figure, a source-degeneration inductor was incorporated. The CMOS variable-gain amplifier achieves measured peak gain of 11.2 dB at 52 GHz, 14.1 dB gain control range, output phase variation lower than 16.5° . The noise figure is 6.2 dB at highest gain and the input 1-dB-compressed power is -18.5 dBm. The dc power consumption is 34.8 mW and the chip size is 0.8 0.58 mm2. The second CMOS VGA is composed of three stages of cascoded variable gain amplifiers, where the combined current-steering and switched attenuator topology was adopted to achieve higher gain control range and lower output phase variation. The measured peak gain is 17.2±0.8 dB in 52-62 GHz with 16.8 dB gain control range, where the output phase variation is lower than 9°. The simulated noise figure is 7 dB at highest gain stage and the input 1-dB-compressed power is -24.6 dBm. The dc power consumption is 24 mW and the chip size is 0.7x0.5 mm2. The single-channel CMOS beamforming receiver is composed of the variable-gain amplifier, Marchand balun, switched 360o-phase shifter, and resistive singly-balanced mixer. The beamforming receiver has the measured conversion gain of -14.9±1.8 dB in 54-63 GHz with gain control range of 18.5 dB. The input 1-dB-compressed power is -28 dBm. The dc power consumption is 44 mW and the chip size is 2.2x0.7 mm2.
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