| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 102 === Dealing the image or video are often accompanied by data computing and data storage. When the number of dealing image or video is very large makes computing excessive and difficult to manage such condition, we call this problem is “Big data analysis”.
When the personal computer (PC) met big data problems, are often faced the execution time too long and use too much storage space problems. The processing program of image or video is usually include a lot of matrix operations. If we send matrix operations of the high repeat degree such as matrix multiplication to field programmable logic gate array (FPGA), it will save a lot of time and storage space.
We send those matrix data from PC to the DDR memory or FPGA evaluation board, and waits FPGA computing is done. Then the result is sent from FPGA back to PC. That environment is one of the priorities of this thesis. We call the environment is “FPGA-based hardware accelerator or FPGA Co-processor platform”.
The application which is running on the FPGA-based hardware accelerator is another priorities of this thesis. Since many image processing algorithms used to matrix multiplication to solve problem such as” Bilateral filter” and “weighted least squares”, those algorithm are used matrix multiplication to enhance the “Edge-Preserving”, so this thesis uses the feature of multiple sets of hardware to design a circuit of matrix multiplication of no size limitation. This thesis will use the FPGA-based hardware accelerator and application of matrix multiplication to accelerate and overcome the bottleneck of PC.
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